In recent several years, ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) concept. An SoC IC includes various reusable functional blocks, such as microprocessors, interfaces, memory arrays, and DSPs (digital signal processors). Such pre-designed functional blocks are commonly called "cores".
FIG. 1 is a schematic diagram showing an example of inner structure of such an SoC IC. In the example of Figure 1, an SoC IC 1 includes a microprocessor core 10, a memory core 3, function specific cores 5-7, a phase lock loop (PLL) core 8, and a test access port (TAP) 9. How to test such embedded cores is a new and complex problem in IC testing. The present invention is directed to a method and structure for testing such embedded cores, such as memory cores, microprocessor and microcontroller (hereinafter "microprocessor") cores, or other function specific cores in an SoC IC.
Microprocessor testing is considered one of the most complex problem in IC testing. In general, an automatic test equipment (ATE) such as an IC tester is commonly used for testing a microprocessor. An IC tester provides a test pattern to the microprocessor under test and the resultant response of the microprocessor is evaluated by expected value data. Because the recent microprocessors have dramatically improved their performance, such as operating speeds, density, functionality, and pin counts, an IC tester for testing such microprocessors needs to be very large scale, high speed, and accordingly very expensive. For example, such an IC tester has several hundreds or more test pins (test channels), each of which includes a pattern generator, timing generator and a frame processor, resulting in a very large and high cost system.
In other approach, various design-for-test (DFT) and built-in self-test (BIST) schemes such as scan, partial scan, logic BIST, scan-based BIST are used to test various logic blocks within a microprocessor. The main problem in these approaches is the requirement of large amount of additional hardware area (extra logic circuits) to implement the test logic. For example, scan implementation in general requires approximately 10% area overhead and scan-based BIST requires approximately 10-15% area overhead on top of the scan implementation. This large area overhead causes larger die, which results into smaller number of dies per wafer, lower yield and higher cost.
In addition, these test schemes also cause a 5-10% performance penalty. Typically, such a performance penalty is a signal propagation delay in the microprocessor because of the additional hardware overhead in the microprocessor. For example, in the scan implementation, each flip-flop circuit in the microprocessor is preceded by a selector (multiplexer) to selectively provide the flip-flop either a scan-in signal or a normal signal. Such an additional selector causes a delay time in the overall performance of the flip-flop circuit. Thus, the design-for-test and built-in self-test schemes adversely affect the microprocessor's performance, such as an operating speed because of the signal propagation delays.
Large embedded (on-chip) memories are the key components in SoC ICs. These embedded memories implement register files, FIFOs (first-in-first-out), data-cache, instruction-cache, transmit/receive buffers, storage for texture processing, etc. Testing of embedded memories is generally done by one of the following methods:
(1) Direct application of test patterns to an embedded memory under test by an IC tester while accessing the memory through an I/O multiplexing: This method requires modification in the I/Os (input/output) of an SoC by adding a multiplexer therein. Due to this extra multiplexer, there is a permanent penalty, for example, a signal propagation delay, in the performance of the SoC IC. The test patterns are generated by an IC tester's pattern generator such as an ALPG (algorithmic pattern generation) unit. However, due to the multiplexer at the I/Os, the actual test patterns require serialization (parallel to serial conversion) of the ALPG patterns, which increases test complexity, test time and many time losses of at-speed testing.
(2) Test application to an embedded memory under test through local boundary scan or a collar register: This method adds a wrapper (boundary scan or shift-register type wrapper) to an embedded memory to be tested. Thus, the data transfer rate to and from the memory under test slows down by the time equal to the delay of the wrapper. Moreover, during testing, the test patterns are serially shifted-in and response is serially shifted-out. Thus, the test time increases significantly and at-speed testing is not possible.
(3) Memory built-in self-test (BIST): This method requires an additional inner circuit for on-chip test generation and response evaluation. This method is the costliest in terms of hardware overhead (additional chip area). The commercially available memory built-in self-test methods require about 3-4% area overhead for a 16K-bits memory. Also, due to additional circuit parasitic, about 1-2% performance penalty, such as signal propagation delays, occurs in memory read/write operations.
(4) Through ASIC functional test: For some small memory, ASIC vendors include simple write/read operations in the ASIC functional test. Most of the time, 1010 . . . 10 pattern is written and read. Generally, this method is applicable to only small memories and extensive testing is not done by this method.
Because the memory built-in self-test causes very little performance penalty at the chip's I/Os, only about 1-2% penalty in the memory read/write operations and provides an acceptable test time, the memory built-in self-test is increasingly used for embedded memories in system-on-chips. Various types of memory built-in self-test methods are available in the market. However, all the known memory built-in self-test methods are very costly in-terms of hardware overhead and allow only a limited number of memory test algorithms. Another limitation of these methods is that if fault diagnosis is desired, these methods require a significantly large amount of additional hardware to identify the failed bit locations.
As has been foregoing, the conventional test approach using the IC tester or design-for-test scheme is not cost-effective for testing embedded cores in a large scale integrated circuit such as an SoC IC.